1. Field of the Invention
The present invention relates to a drive circuit, an operation state detection circuit, and a display device, and more particularly to a drive circuit for driving a capacitive load such as a liquid-crystal panel and to an operation state detection circuit and a display device.
2. Description of the Related Art
In recent years, liquid-crystal panels has diversified and found application in a wide variety of fields from small panels for portable games to panels for large-screen TV sets. Accordingly, it is necessary that the drive circuits for driving the liquid-crystal panels perform the desired operations under various load conditions.
Not only in the case of liquid-crystal panels of different shapes, but also when the liquid-crystal panels are of the same shape, there is manufacturing variations between liquid-crystal panels in the manufacturing process. As a result, the load conditions of drive circuits for driving the liquid-crystal panels differ for each drive line of the liquid-crystal panel, that is, for each output of the drive circuit. Furthermore, in the drive circuits, when the number of horizontal dots of the liquid-crystal panel is not divisible by the number of outputs of the drive circuits, the redundant output terminals are used in an open state, and in this case, the load conditions also differ for each output of the drive circuit. Furthermore, property evaluation of drive circuits is conducted with a tester in the manufacturing process of the drive circuits, and the load conditions during such evaluation with the tester are completely different from the load conditions of the liquid-crystal panel. Therefore, there are a variety of different load conditions of the drive circuit, and those conditions sometimes differ for each output terminal even in a single drive circuit.
An operational amplifier connected in a voltage follower fashion is generally used as an output circuit provided in the output section of such drive circuits. In the operational amplifiers, phase margin changes due to fluctuations of the load conditions of driving. If the phase margin in an operational amplifier used in a drive circuit is deteriorated, the operational amplifier starts oscillating and causing defects in the liquid-crystal panel displays. For this reason, operational amplifiers used in drive circuits are designed in consideration of all the conditions of loads to be connected to the output of the above-described drive circuits.
Phase compensation by a mirror capacitance is generally known as one means for increasing the phase margin of operational amplifiers. Phase compensation by a mirror capacitance separates the first pole and second pole of an operational amplifier to realize the desired phase characteristics. In this method the higher is the phase compensation capacitance, the larger is the phase margin. If the phase is compensated for with a capacitance value sufficient from the standpoint of the above-described fluctuations of load conditions, the phase margin of the operational amplifier increases and no oscillations occur.
However, drive circuits require low power consumption and high-load drive capability at the same time. Reduction of power consumption and improvement of high-load drive capability of the operational amplifiers used in the output circuits are mandatory conditions for reducing power consumption and improving high-load drive capability of the drive circuits. The slew rate (SR), differential stage current (Id) and phase compensation capacitance value (Cc) of an operational amplifier satisfy the relationship of the following Formula 1:SR=ld/Cc  [Formula 1]
Thus, increasing the phase compensation capacitance value in order to maintain the phase margin of an operational amplifier degrades the drive capability. In order to prevent the drive capability from being degraded, the power consumption of the operational amplifier has to be increased. In other words, from the standpoint of realizing a low power consumption and high-load drive capability, it is desired that the phase compensation capacitance value of the operational amplifier be small. A technique to connect a resistor in series to the capacitive load is known to increase the phase margin of an operational, amplifier with respect to a capacitive load.
Here, the mechanism of oscillations in an operational amplifier will be explained. FIG. 5 is a basic block-diagram of a general feedback circuit. Referring to FIG. 5, the reference numeral 24 designates an operational amplifier and the reference numeral 23 designates a feedback section. As shown in FIG. 5, in the case of feedback of the operational amplifier 24, the closed-loop voltage gain will be represented by the following Formula 2, where Ao stands for an open-loop voltage gain of the operational amplifier 24 and β stands for a feedback factor of the feedback section 23:
                    Ac        =                              vo            vi                    =                                    -              Ao                                      1              +                              Ao                ⁢                                                                  ⁢                β                                                                        [                  Formula          ⁢                                          ⁢          2                ]            
From this formula it follows that when Aoβ=−1, that is, when |Ao|=|1/β|, if the phases of input and output are inverse, then the operational amplifier starts oscillating due to the feedback. Further, FIG. 6 shows a Bode diagram representing the frequency characteristic of the feedback circuit shown in FIG. 5. In the Bode diagram shown in FIG. 6, if the gradient difference is 40 dB/dec or higher at the point where Ao and 1/β intersect, the operational amplifier 24 oscillates at a frequency fo of the intersection point.
FIG. 7 shows a block diagram illustrating an example of the conventional feedback circuit. An operational amplifier used in the output circuit of a drive circuit, is used in a voltage follower connection as shown in FIG. 7. Referring to FIG. 7, the reference numeral 25 designates an operational amplifier, 26—an output resistance Ro of the operational amplifier, 27—a resistor RL for improving the phase margin, and 28—a load capacitance CL. In this example, 1/beta is represented by the following Formula 3, and the Bode diagram assumes the shape shown in FIG. 8.
                              1          β                =                              vo            vi                    =                                                    Ro                +                                  (                                      RL                    +                                          1                      sCL                                                        )                                                            RL                +                                  1                  sCL                                                      ⁢                                                  ⁢                                                  =                                                            Ro                  +                  RL                                RL                            ·                                                (                                      s                    -                                          1                                              CL                        ⁡                                                  (                                                      Ro                            +                            RL                                                    )                                                                                                      )                                                  (                                      s                    -                                          (                                              -                                                  1                          CLRL                                                                    )                                                        )                                                                                        [                  Formula          ⁢                                          ⁢          3                ]            
As shown in FIG. 8, if the resistor RL is connected in series with the load capacitance CL of the operational amplifier, the phase margin is improved and the slope of 1/β decreases with the increase in the resistance value of the connected resistor RL. Thus, if the resistance value of the resistor RL increases, the gradient difference of 1/β and Ao decreases. Therefore, the effect of improving the phase margin becomes more significant.
However, as described hereinabove, the drive circuits are required to have both low power consumption and high-load drive capability at the same time. In other words, it is required to decrease power consumption and improve a high-load drive capability of operational amplifiers used in output circuits. Connecting a resistor in series to the load of the operational amplifier causes deterioration of the drive capability of the operational amplifier, and power consumption of the operational amplifier has to be increased to prevent the drive capability from deteriorating. In other words, in order to realize low power consumption and high-load drive capability, it is desirable to use a small resistance value of the resistor connected in series with the load of the operational amplifier.
A method is known in which the resistance value of the load connected to the operational amplifier is switched to satisfy the afore-described requirement. FIG. 9 is a block diagram illustrating a configuration example of a drive circuit and a display panel of the conventional liquid-crystal display device. FIG. 10 is a block diagram illustrating a configuration example of the conventional drive circuit. The explanation will be conducted below with reference to those drawings.
As shown in FIG. 9, the liquid-crystal display device comprises a control circuit 29, a gradation voltage power source 30, a scanning line drive circuit 31, a data line drive circuit 32, and a display panel 33 driven by the scanning line drive circuit 31 and data line drive circuit 32.
Here, the display panel 33 is an active matrix color liquid-crystal panel that uses thin-film MOS transistors (TFT) 38 as switch elements. In this panel, pixels are arranged in rows and columns at the intersection points of scanning lines 35 and data lines 34 provided with respective prescribed distances in the row direction and column direction. The pixel comprises the liquid-crystal capacitance 36 that is an equivalent capacitive load and TFT 38 whose gate is connected with the scanning line 35, which are connected in series between the data lines 34 and a common electrode line 37.
Scanning pulses generated by the scanning line drive circuit 31 are applied to each row of scanning line 35 of the display panel 33 based on the horizontal synchronization signals and vertical synchronization signals. In a state in which a common potential Vcom is applied to the common electrode line 37, an analog data signal generated for each color by the data line drive circuit 32 based on the digital display data is applied to each column of data line 34 of the display panel. As a result, color text or images are displayed on the display panel 33.
The data line drive circuit 32 will be described below. The data line drive circuit 32 comprises a D/A conversion circuit 39 for converting (D/A converting) respective digital signals to analog signals for display data of each column by selecting one gradation level of voltage, and an output circuit 41 changing the impedance to drive each data line 34, and outputting an analog display data signal.
As shown in FIG. 9 and FIG. 10, the output circuit 41 comprises a plurality of operational amplifiers 401 with rail-to-rail input/output and respectively connected in a voltage follower fashion, a switch 402 connected between the output Vout of the data line drive circuit 32 and output terminal Sout of the operational amplifier 401, a switch 403 connected in parallel to the switch 402, and a common bias circuit 40 for supplying a common bias voltage to the operational amplifiers 401. The switch 402 becomes a resistor of a very low resistance value (low resistor) when it is switched ON, and the switch 403 becomes a resistor of a very high resistance value (high resistor) when it is switched ON. For example, the switch 402 is switched ON when the external control signal S1 is at a low level, and the switch 403 is switched ON when the external control signal S2 is at a high level.
FIG. 11 is a timing chart illustrating the operation of the drive circuit. For example, in the t2 duration shown in FIG. 11, that is, when the operational amplifier 401 is in a load drive state, both the switch 402 of a low resistance value and the switch 403 of a high resistance value are controlled by the external control signals S1, S2 so as to be switched ON. As a result, the gradation voltage that was outputted from the D/A conversion circuit 39 and inputted to the operational amplifier 401 is inputted through the switch 402 and switch 403 into the display panel 33 and drive will be conducted to the desired voltage.
At this time, because the switch 402 and switch 403 are connected in parallel and the resistance value of the switch 402 is extremely low, the total resistance value of the output switches (switch 402 and switch 403) of the operational amplifier 401 assumes a value almost equal to the resistance value of the switch 402. For this reason, the output switch of the operational amplifier 401 has a low resistance and can have high driving capability. Reducing the resistance value of the output switch of the operational amplifier 401 realizes a high drive capability, but degrades the phase margin of the operational amplifier 401. However, when the liquid-crystal panel load is driven, the operational amplifier 401 is in a transient state and the phase margin is not required to be taken into account. For this reason, reducing the resistance value of the output switch realizes high drive capability, but causes not problems.
Further, in the durations other that t1 and t2 shown in FIG. 11, that is, when the operational amplifier 401 is in a stationary state, the first switch 402, which has a low resistance, and the second switch 403, which has a high resistance, are controlled by the external control signals S1, S2 so as to be switched OFF and ON, respectively. As a result, the gradation voltage inputted from the D/A conversion circuit 39 into the operational amplifier 401 is held and outputted via the switch 403, which has a high resistance.
As described hereinabove, connecting a high-resistance element between the output of the operational amplifier 401 and the load increases the phase margin of the operational amplifier 401 and reduces the susceptibility to the effect of load condition fluctuations. Thus, when the operational amplifier 401 is in a stationary state, the second switch 403, which has a high resistance, plays a role of the resistor for improving the phase margin. Therefore, good phase margin can be maintained even against load fluctuations.
It has now been discovered that the problem associated with the data line drive circuit 32 representing the above-described conventional technology is that the timing of the control signal for conducting switching of the resistance value is constant and can correspond only to specific load conditions in order to control identically all the outputs of the data line drive circuit 32.
With the conventional technology, the above-mentioned external control signals S1, S2 are usually timing generated according to the internal clock in a logical circuit (not shown in the figure) provided inside the data line drive circuit 32, and a plurality of the operational amplifiers 401 are controlled together thereby. Because the operation of this logical circuit is determined by the process for the fabrication of the data line drive circuit 32, the control timing of the external control signals S1, S2 is also determined at the same time.
Thus, the control timing of the external control signal S1, S2 becomes the timing designed in advance by the designer of the data line drive circuit 32 under certain assumptions relating to load conductions. Therefore, it is impossible to deal with the unexpected load conditions. For example, the slope of the output signal Vout of the output circuit 401 during load driving fluctuates according to the load conditions and the length of the load drive duration t2 also fluctuates. Therefore, when the operational amplifier 401 is designed, the design has to provide a certain spare amount for the phase margin by taking into account the spread of load conditions.
Further, the load conditions, such as the spread in load between the data lines in the process for the manufacture of the liquid-crystal panel and the difference in voltage between the outputs outputted by the output circuit 401 of the data line drive circuit 32, are different for each output of the operational amplifier. Furthermore, in the data line output circuits 32, all the outputs are sometimes not connected to the liquid-crystal panels for certain resolutions of the liquid-crystal panel.
For example, in the case of a liquid-crystal panel with an XGA (1024×768) resolution using a 384-output data line drive circuit 32, all the outputs of the data line drive circuit 32 are connected to the liquid-crystal panel by using eight data line drive circuits 32. In the case of a liquid-crystal panel with an UXGA (1600×1200) resolution, a total of 13 data line drive circuits 32 are used, but in one of the data line drive circuits 32, 192 outputs of 384 outputs are not connected to the liquid-crystal panel and used in an open state. In other words, 192 outputs of operational amplifiers 401 of data line drive circuits 32 drive the liquid-crystal panel load, which is a heavy load, and the remaining 192 outputs drive a parasitic component load, which is a light load.
In this case, with the system of controlling together a plurality of operational amplifiers 401, as in the conventional data line drive circuits 32, it is impossible to deal with the fluctuations of load conditions of each pin. Because those operational amplifiers 401 have to be designed so as to have a good phase margin under all of a variety of load conditions, the design has to provide a certain spare amount for the phase margin by taking into account this variety of load conditions.
Holding such spare amount for the phase margin of the operational amplifier 401 requires a large phase compensation capacitance. The operational amplifiers 401 of the drive circuits of display devices are arranged at a ratio of 400 or more per one chip of the data line drive circuit 32. Therefore, providing a large phase compensation capacitance for the operational amplifiers 401 hinders the increase in the degree of integration. Furthermore, a large phase compensation capacitance causes the decrease in the drive capability of the operational amplifiers 401, and the increase in power consumption is indispensable to maintain the drive capability of the operational amplifiers 401.
Furthermore, even when the external control signals are controlled independently from the data line control circuit 32, it is difficult to take into account spread of various types and usage conditions and to determine accurately the load conditions of operational amplifiers. Furthermore, wiring for control signals increases, thereby hindering the increase in the degree of integration.
Drive circuits disclosed in Japanese Unexamined Patent Publication Nos. 11-85113 (Japanese Patent No. 3488054) and 2000-295044 are known as the conventional drive circuits for liquid-crystal display devices.
Thus, the problem associated with the conventional drive circuits of the liquid-crystal display devices is that the timing of control signals for switching the resistance value is constant, the operation that can be conducted to control all the multiple outputs identically corresponds only to specific load conditions, and the phase margin and drive capability are sometimes degraded by the load conditions.